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Senior Research Fellow (specialize in FPGA design engineering)

Senior Research Fellow (specialize in FPGA design engineering)

The Centre for Quantum Technologies (CQT) is a research centre of excellence at the National University of Singapore doing cutting-edge theoretical and experimental science. CQT is located on the campus of the National University of Singapore and offers a friendly, international work environment. Learn more about CQT at

At CQT we are developing next generation hardware for Quantum Processors. Our team is composed of researchers with various backgrounds in science and we work at the spearhead towards developing technologies enhancing current quantum processors.


Job description:

The precise and fast control of a Quantum Processor is of highest priority in any scalable approach for quantum computing. FPGA’s play a vital role to tackle this challenge. Employing state of the art FPGA’s designed for microwave applications, we are able to generate versatile microwave pulse sequences as well as capture microwave signals to directly process them on the FPGA and optimize the pulse sequence for the qubit control.

We are looking for a Senior Research Fellow (specialize in FPGA design engineering), you will work closely with quantum processor hardware team as well as with the quantum software team. Your goal will be to design/verify and deliver robust solutions tailored to the problem set. Your skill set should reach from system level design to implementing and characterization of the individual components. You should be familiar with latency critical designs.


Duties & Responsibilities:


  • Developing FPGA control solutions to for advanced quantum processors
  • System and block level design and verification using VHDL or Verilog
  • Ensuring designs meet timing, utilisation and power requirements
  • Low-level driver development ideally using Python.
  • Documenting design ideas, specifications and test results.



Qualifications & Skills:


  • Minimum Qualification : PhD’s degree in engineering or equivalent
  • 3+ years of commercial FPGA design and development experience.
  • Proven track record of system and block level design and verification using HDLs, (Verilog).
  • Proficiency with FPGA tools, (Vivado), i.e. using IP blocks, defining constraints, and analysing outputs.
  • Experience in the design and implementation of digital signal processing for FPGA.

Remuneration will commensurate with the candidate’s qualifications and experience.

Duration of Contract: up to 1 year (subject to funding availability and performance appraisal)

For more information about Rainer Dumke's research interests, please visit his homepage at

Applications can be submitted via the link below and should contain: the latest CV, and letter of recommendation (if any).

We regret that only shortlisted candidates will be notified.



Interested applicants may apply the position click here.

Closing Date: 30-Jun, 12:00AM.